# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 07:45:51 April 11, 2020 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # Microcomputer_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # # Project-Wide Assignments # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:37:40 MARCH 29, 2019" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name VHDL_FILE Components/M6809/cpu09.vhd set_global_assignment -name HEX_FILE ROMS/6809/EXT_BASIC_NO_USING.hex set_global_assignment -name VHDL_FILE Components/TERMINAL/SansBoldRom.vhd set_global_assignment -name VHDL_FILE Components/TERMINAL/SansBoldRomReduced.vhd set_global_assignment -name VHDL_FILE Components/TERMINAL/DisplayRam2K.vhd set_global_assignment -name VHDL_FILE Components/TERMINAL/DisplayRam1K.vhd set_global_assignment -name VHDL_FILE Components/TERMINAL/CGABoldRom.vhd set_global_assignment -name VHDL_FILE Components/TERMINAL/CGABoldRomReduced.vhd set_global_assignment -name VHDL_FILE Components/TERMINAL/SBCTextDisplayRGB.vhd set_global_assignment -name VHDL_FILE Components/IO/OutLatch.vhd set_global_assignment -name VHDL_FILE Components/UART/Toggle_On_FN_Key.vhd set_global_assignment -name VHDL_FILE Components/UART/bufferedUART.vhd set_global_assignment -name VHDL_FILE ROMS/6809/M6809_EXT_BASIC_ROM.vhd set_global_assignment -name VHDL_FILE IntRAM16K.vhd set_global_assignment -name SOURCE_FILE Microcomputer_assignment_defaults.qdf set_global_assignment -name VHDL_FILE Microcomputer.vhd set_global_assignment -name CDF_FILE output_files/Chain1.cdf set_global_assignment -name CDF_FILE output_files/Chain2.cdf set_global_assignment -name SIGNALTAP_FILE output_files/stp_post.stp set_global_assignment -name QIP_FILE dhrProbe.qip # Pin & Location Assignments # ========================== set_location_assignment PIN_99 -to ps2Clk set_location_assignment PIN_98 -to ps2Data set_location_assignment PIN_100 -to hSync set_location_assignment PIN_101 -to vSync set_location_assignment PIN_24 -to clk set_location_assignment PIN_84 -to n_reset set_location_assignment PIN_120 -to videoR0 set_location_assignment PIN_121 -to videoR1 set_location_assignment PIN_124 -to videoR2 set_location_assignment PIN_125 -to videoR3 set_location_assignment PIN_126 -to videoR4 set_location_assignment PIN_111 -to videoG0 set_location_assignment PIN_112 -to videoG1 set_location_assignment PIN_113 -to videoG2 set_location_assignment PIN_114 -to videoG3 set_location_assignment PIN_115 -to videoG4 set_location_assignment PIN_119 -to videoG5 set_location_assignment PIN_103 -to videoB0 set_location_assignment PIN_104 -to videoB1 set_location_assignment PIN_105 -to videoB2 set_location_assignment PIN_106 -to videoB3 set_location_assignment PIN_110 -to videoB4 set_location_assignment PIN_88 -to switch0 set_location_assignment PIN_91 -to switch1 set_location_assignment PIN_90 -to switch2 set_location_assignment PIN_13 -to ~ALTERA_DATA0~ set_location_assignment PIN_12 -to ~ALTERA_DCLK~ set_location_assignment PIN_8 -to ~ALTERA_FLASH_nCE_nCSO~ set_location_assignment PIN_6 -to ~ALTERA_ASDO_DATA1~ set_location_assignment PIN_86 -to rxd set_location_assignment PIN_87 -to txd # Classic Timing Assignments # ========================== set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 # Analysis & Synthesis Assignments # ================================ set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name TOP_LEVEL_ENTITY Microcomputer # Fitter Assignments # ================== set_global_assignment -name DEVICE EP4CE6E22C8 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hSync set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to n_reset set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ps2Clk set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ps2Data set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vSync set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to videoB4 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to videoG5 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to videoR4 set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" # EDA Netlist Writer Assignments # ============================== set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" # Assembler Assignments # ===================== set_global_assignment -name USE_CONFIGURATION_DEVICE OFF # Simulator Assignments # ===================== set_global_assignment -name SIMULATION_MODE TIMING set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/altera/13.0sp1web/M6809_VGA_PS2_UART_IntRAM(16K)/Waveform.vwf" # SignalTap II Assignments # ======================== set_global_assignment -name ENABLE_SIGNALTAP ON set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp_post.stp # Power Estimation Assignments # ============================ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" # Advanced I/O Timing Assignments # =============================== set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall # start EDA_TOOL_SETTINGS(eda_simulation) # --------------------------------------- # EDA Netlist Writer Assignments # ============================== set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation # end EDA_TOOL_SETTINGS(eda_simulation) # ------------------------------------- # start AUTO_INSERT_SLD_NODE_ENTITY(auto_signaltap_0) # --------------------------------------------------- # SignalTap II Assignments # ======================== set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to cpuClock -section_id auto_signaltap_0 set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT trigger_in -to switch2 -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=1" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=1" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=21" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "cpu091:cpu1|fic" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "cpu091:cpu1|pc[0]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "cpu091:cpu1|pc[10]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "cpu091:cpu1|pc[11]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "cpu091:cpu1|pc[12]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "cpu091:cpu1|pc[13]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "cpu091:cpu1|pc[14]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "cpu091:cpu1|pc[15]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "cpu091:cpu1|pc[1]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "cpu091:cpu1|pc[2]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "cpu091:cpu1|pc[3]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "cpu091:cpu1|pc[4]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "cpu091:cpu1|pc[5]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "cpu091:cpu1|pc[6]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "cpu091:cpu1|pc[7]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "cpu091:cpu1|pc[8]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "cpu091:cpu1|pc[9]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "cpu09:cpu1|sp[0]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "cpu09:cpu1|sp[10]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "cpu09:cpu1|sp[11]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "cpu09:cpu1|sp[12]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "cpu09:cpu1|sp[13]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "cpu09:cpu1|sp[14]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "cpu09:cpu1|sp[15]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "cpu09:cpu1|sp[1]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "cpu09:cpu1|sp[2]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "cpu09:cpu1|sp[3]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "cpu09:cpu1|sp[4]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "cpu09:cpu1|sp[5]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "cpu09:cpu1|sp[6]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "cpu09:cpu1|sp[7]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "cpu09:cpu1|sp[8]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "cpu09:cpu1|sp[9]" -section_id auto_signaltap_0 set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to n_aciaCS~0 -section_id auto_signaltap_0 set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to n_videoInterfaceCS~0 -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "cpu091:cpu1|fic" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "cpu091:cpu1|pc[0]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "cpu091:cpu1|pc[10]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "cpu091:cpu1|pc[11]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "cpu091:cpu1|pc[12]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "cpu091:cpu1|pc[13]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "cpu091:cpu1|pc[14]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "cpu091:cpu1|pc[15]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "cpu091:cpu1|pc[1]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "cpu091:cpu1|pc[2]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "cpu091:cpu1|pc[3]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "cpu091:cpu1|pc[4]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "cpu091:cpu1|pc[5]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "cpu091:cpu1|pc[6]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "cpu091:cpu1|pc[7]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "cpu091:cpu1|pc[8]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "cpu091:cpu1|pc[9]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "cpu09:cpu1|sp[0]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "cpu09:cpu1|sp[10]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "cpu09:cpu1|sp[11]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "cpu09:cpu1|sp[12]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "cpu09:cpu1|sp[13]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "cpu09:cpu1|sp[14]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "cpu09:cpu1|sp[15]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "cpu09:cpu1|sp[1]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "cpu09:cpu1|sp[2]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "cpu09:cpu1|sp[3]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "cpu09:cpu1|sp[4]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "cpu09:cpu1|sp[5]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "cpu09:cpu1|sp[6]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "cpu09:cpu1|sp[7]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "cpu09:cpu1|sp[8]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "cpu09:cpu1|sp[9]" -section_id auto_signaltap_0 set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to n_aciaCS~0 -section_id auto_signaltap_0 set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to n_videoInterfaceCS~0 -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=35" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=35" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=36632" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=55037" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=sld_reserved_m6809_vga_16K_auto_signaltap_0_1_acab," -section_id auto_signaltap_0 # end AUTO_INSERT_SLD_NODE_ENTITY(auto_signaltap_0) # ------------------------------------------------- # --------------------------- # start ENTITY(Microcomputer) # Fitter Assignments # ================== set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hSync set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to n_reset set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to ps2Clk set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to ps2Data set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vSync set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to clk set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoB4 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoG5 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoR4 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoB3 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED2 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED3 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED4 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to rts set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to rxd set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to switch0 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to switch1 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to switch2 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to txd set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoB0 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoB1 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoG0 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoB2 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoG2 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoG1 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoG4 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoG3 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoR0 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoR1 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoR2 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to videoR3 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to ~ALTERA_DATA0~ set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to ~ALTERA_FLASH_nCE_nCSO~ set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to ~ALTERA_ASDO_DATA1~ # start DESIGN_PARTITION(Top) # --------------------------- # Incremental Compilation Assignments # =================================== set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(Microcomputer) # ------------------------- set_location_assignment PIN_133 -to DSEN1 set_location_assignment PIN_135 -to DSEN2 set_location_assignment PIN_136 -to DSEN3 set_location_assignment PIN_137 -to DSEN4 # set_location_assignment PIN_143 -to LEDSEGA set_location_assignment PIN_144 -to LEDSEGB set_location_assignment PIN_1 -to LEDSEGC set_location_assignment PIN_141 -to LEDSEGD set_location_assignment PIN_142 -to LEDSEGE set_location_assignment PIN_138 -to LEDSEGF set_location_assignment PIN_2 -to LEDSEGG set_location_assignment PIN_3 -to LEDSEGH # set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name CDF_FILE output_files/Microcomputer_jic.cdf set_global_assignment -name SLD_FILE "C:/altera/13.0sp1web/M6809_VGA_PS2_UART_IntRAM(16K)/output_files/stp_post_auto_stripped.stp"